Pilot line on advanced Fully Depleted Silicon On Insulator technologies targeting 7nm
HORIZON JU Research and Innovation Actions
Basic Information
- Identifier
- HORIZON-JU-Chips-2023-RIA-CPL-2
- Programme
- Call for proposals for Set-up, integration and process development
- Programme Period
- 2021 - 2027
- Status
- Closed (31094503)
- Opening Date
- February 1, 2024
- Deadline
- February 29, 2024
- Deadline Model
- single-stage
- Budget
- €70,000,000
- Min Grant Amount
- –
- Max Grant Amount
- €70,000,000
- Expected Number of Grants
- 1
- Keywords
- HORIZON-JU-Chips-2023-RIA-CPL-2HORIZON-JU-Chips-2023-RIA-CPL
Description
With the entry into force of the Chips Act on 21 September 2023, the Chips for Europe Initiative (‘Initiative’) has been established.
Under this Initiative Chips JU is launching this Call to enhance existing and develop new advanced pilot lines across the Union to enable development and deployment of cutting-edge semiconductor technologies and next-generation semiconductors.
Eligibility & Conditions
General conditions
General conditions
1. Admissibility conditions: described in the Amended Chips JU Work Programme 2023
Page limits and layout: described in the Amended Chips JU Work Programme 2023
2. Eligible countries: described in the Amended Chips JU Work Programme 2023
3. Other eligibility conditions: described in the Amended Chips JU Work Programme 2023
4. Financial and operational capacity and exclusion: described in the Amended Chips JU Work Programme 2023
-
Award criteria, scoring and thresholds
-
Submission and evaluation processes
-
Indicative timeline for evaluation and grant agreement
6. Legal and financial set-up of the grants: described in the Amended Chips JU Work Programme 2023
Specific conditions
7. Specific conditions: described in the Amended Chips JU Work Programme 2023
Documents
Call documents: Submission
Template HE - National Budgets Table
Tpl_Application_Form_(Part B)_HE
Work Programme and annexes
Chips JU Amended Work Programme 2023
Appendix2&4 Annex1 Application Form
Appendix2&4 Annex2 TemplateHostingAgreement
Appendix2&4 Annex4 Model - Letter of Intent
Support & Resources
For help related to this call, please contact: the Chips JU Calls Team @ [email protected]
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Latest Updates
REMINDER Call Deadline and Submissions:
The Deadline for submission is today 29 February 2024 at 17:00 Brussels time.
IMPORTANT : Only proposals submitted in each of the three interrelated calls will be eligible for evaluation
File Size increase:
Please be informed that the file size has been increased to 50MB for the Part B Submission
Page limit:
Please note that there are no page limits for the application but the consortia are encouraged to limit the narrative part of the application to 200 pages excluding the tables that are expected.
The proposed pilot line shall work at all levels of the main technological steps:
• Development of the 10nm to 7nm FD-SOI technology modules for enhancing the performances of the current FD-SOI technology, including RF applications, through reducing the transistor size. The main technologies to be developed shall be: the enhancement of the carrier mobility, the optimization of the transistor process, the development of the Middle-of-Line (MoL) modules and the development of Back-End-of-Line (BEOL) process modules. They should be performed through a strong interaction between the process and design teams in order to optimize the FD-SOI device performances, and to deliver the PDKs for each developed technology and process modules.
• Development of the additional process modules.
o Memories: The Pilot Line platform should be enhanced by adding in the metal interconnections. These additions can offer new ranges of applications and would allow breakthroughs like in-memory computing. Several memory NVM options (PCRAM, FeRAM, OxRAM, MRAM etc.) will have to be proposed to the pilot line partners, by themselves or in collaboration with other pilot lines.
o 3D options: The Pilot Line should offer design environments compatible with new 3D architectures, chip-on-wafer and wafer-to-wafer alignment technologies and efficient bonding techniques. 3D option based on monolithic sequential integration should also be proposed to further improved performances and decreased cost.
• Delivery of updated PDKs
▪ Once the technology and additional process module will be mature enough, the proposed pilot line will have to continuously deliver updated PDKs of the developed technologies for technology assessment.
▪ Any stakeholder must have access to the PDKs, describing the updated 10-7nm FD-SOI technology and the additional modules through the Design Platforms, the Competence Centers and/or directly to the pilot line.
• Realization of circuits through Multi-Project-Wafers (MPW) runs for European partners, according to an operational and access policy defined for the pilot line for the collaboration with those stakeholders.
The access policy from the different stakeholders to the pilot line should be defined in the proposal according to fair and non-discriminatory principles.
During the whole duration of the pilot line, the hosting entity and other partners should provide training to any European partner interested in designing devices based on FD-SOI technology in order to use the full benefits of this technology, as well as for students for up- and re-skilling in order to attract new talents in the European semiconductor industry.
Collaborations: The proposed FD-SOI pilot line must facilitate the collaboration with other pilot lines, with design platforms and competence centres to allow contributions from other stakeholders that develop a strong expertise in a specific domain related to the topics of this pilot line.