RISC-V Automotive Hardware Platform

The overall ambition of this call is to develop in-vehicle demonstrators capable of PetaOPS computing taped-out on leading-edge processes. Proposals are expected to significantly bolster the development of a high-performance automotive RISC-V reference hardware platform, encompassing the following crucial components:

1. High-Performance RISC-V Automotive Application Processors: Launch of high-performance, RISC-V application processors designed for automotive applications. These processors will include advanced computer architecture techniques, multi-core configurations and support for high-bandwidth memory interfaces, catering to the complex computing demands of autonomous driving systems.
2. AI and ML Automotive Accelerators: Development of AI and ML accelerators with specialised ISA extensions for efficient data-intensive computations. These accelerators shall be optimised for automotive applications, supporting advanced AI models with a focus on energy efficiency and real-time processing capabilities.
3. System Integration and Interfacing: Establishment of a coherent system architecture integrating RISC-V cores, AI accelerators, memory and system peripherals. This includes the use of 2.5D/3D integration, the development of high-bandwidth interconnects with Quality of Service (QoS) and shared cache memories to support the high memory bandwidth required by advanced automotive applications. System 2.5/3D integration will be developed in this programme’s call on heterogeneous integration for automotive.
4. Software Tools and Libraries: Development of a comprehensive tool-chain to support the developed RISC-V hardware. This includes compilers, binary utilities, integrated development environments (IDEs), and runtime libraries tailored for automotive applications, ensuring ease of programming and optimal performance. Hardware-software co-design is encouraged.
5. Collaboration with the Software Defined Vehicle Initiative: Strengthening of the open-source ecosystem through collaboration between hardware and software development, and automotive industry stakeholders. This collaborative effort will focus on alignment with other Chips Joint Undertaking projects on the Software Defined Vehicle regarding automotive standardised interfaces, middleware and APIs to facilitate seamless integration and interoperability.
6. Benchmarking and Quality Assurance: Implementation of benchmarking techniques to assess the performance, safety, and security of the RISC-V platforms. This will ensure compliance with automotive industry standards and regulations, paving the way for the adoption of RISC-V processors in safety-critical automotive applications.