A Pan-European infrastructure for Chips Design Innovation

Proposals are expected to address the following expected outcomes:

Here are the outcomes with the title capitalisation removed in the bold parts:

• Establish a platform for the European design ecosystem: Created a platform that supports the growth of a European design ecosystem by fostering design reuse, enabling the exploitation of advanced technologies in various application domains, and providing a foundation for deep-tech startups.
• Encourage dissemination of PDKs through the platform: Actively supported foundries in sharing open-source and proprietary technologies, particularly their PDKs, via the platform.
• Streamline access to EDA tools: Simplified and lowered barriers to access commercial and open-source industry-standard EDA tools across various technologies, with a focus on affordability.
• Enhance workforce skills through hands-on experience: Reduced barriers for undergraduate and postgraduate students to gain hands-on IC design experience, complementing their theoretical coursework.
• Provide diverse chip design flows: Offered a variety of chip design flows, supporting multi-vendor configurations where feasible, and assisted users in customising their design workflows.
• Facilitate affordable prototyping access: Enabled academia, research centres, and spinouts to prototype affordably using industrial-grade and emerging technologies, including advanced nodes, mature nodes, open-source solutions, and pilot-line technologies, with pathways to volume production.
• Offer extensive training resources: Delivered comprehensive training resources to up-skill and re-skill students and professionals across a wide range of technologies.
• Train academics and instructors through ‘train-the-trainer’ programmes: Provided targeted training for educators in semiconductor and photonics technologies to improve teaching quality and dissemination.
• Provide a platform for open-source IP exchange: Established a platform for sharing open-source IP, fostering collaboration and reuse.
• Support students in gaining hands-on chip design experience: Facilitated pre-tertiary and vocational students’ access to open-source tool flows, promoting practical engagement with chip design.
• Ensure access to customer support and leading-edge tools: Simplified access to customer support, IP, and cutting-edge design tools for a broad user base.
• Lower barriers for advanced packaging and integration: Supported users in adopting advanced packaging and heterogeneous integration techniques by reducing entry barriers.
• Enable efficient fabrication and system integration: Facilitated multi-project wafer (MPW) runs and small-volume fabrication of ASICs, photonics, MEMS, sensors, and their integration at the system level, while promoting the adoption of emerging or underutilised technologies such as quantum technologies, photonics, and wide-bandgap materials by academia and SMEs.
• Promote technology offerings from research centres: Supported and highlighted the technology services of research centres with lower TRL (technology readiness level) capabilities.
• Furthermore, particular emphasis should be placed on ensuring the seamless integration of this initiative within the framework of the Chips Act. To this end, proposals must address the following outcomes:
• Collaborate extensively with initiatives under Pillar 1 of the Chips Act such as the Design Platform, competence centres and pilot lines. Particularly by:
  1. collaborating extensively with the Design Platform initiative, including through joint activities;
  2. facilitating academic access to the Chips Act pilot lines;
  3. support competence centres across all EU Member States.
• Implement a comprehensive plan to integrate EUROPRACTICE services into the Chip Act’s Design Platform by the conclusion of this project.