Chiplet for Defence Application

The outcome should contribute to:

• Develop and share a common hardware library of chiplets building blocks.
• Identify EU based building blocks compatible with advanced architecture for defence components.
• Increase competitive advantage to the EDTIB in the domain of components development and integration.
• Increase flexibility of architectures to create multifunctional, systems, able to adapt to capability needs.

A new paradigm is proposed by the development of the so-called “chiplet” approach, where a chiplet is an integrated circuit block that has been specifically designed to work with other chiplets to form more complex integrated systems. This approach can be used for System in Package (SiP) (heterogeneous integration) in which the System is subdivided into functional circuit blocks.

Chiplets offer a new opportunity for defence electronics, overcoming the limitations of generic components like FPGAs (offering a single solution with limited performances) and ASICs (offering high performances but with high development costs due to the specific development). Chiplet architecture offers an interesting opportunity to reduce the development costs thanks to the reuse of existing blocks and to decrease the manufacturing cost thanks to higher yield compared to large monolithic dies. It may also benefit from use of off-the-shelf chiplets to limit development costs and reinforce the resilience of the supply chain. In addition, chiplets-based architectures are scalable: the addition or removal of chiplets enables the performance and/or functionality adjustment of the SiP.

Chiplet technology in combination with heterogeneous packaging has been widely used in increasing performance of commercial CPUs. The chiplet technology combined with heterogeneous packaging offers the possibility to integrate chiplets processed in different technologies into the same package, thus offering the possibility to develop very compact and innovative System in Package.

Specific objective

The objective is to explore the possibilities the chiplet technology in combination with heterogeneous packaging can add to systems used for defence applications. Combining e.g., chiplets made in different technologies (GaN, GaAs, Si etc) and with analogue, mixed analogue/digital and digital functions may lead to new capabilities in processing power and still achieve a reasonable cost level and power consumption. New and/or improved devices can be made by exploring chiplet technology in various fields of defence applications such as, but not limited to: radar systems, Electronic Warfare systems, communication systems, munition applications, signal processing applications.

This call topic contributes to the STEP objectives, as defined in STEP Regulation, in the target investment area of deep and digital technologies.

This topic aims to explore the development and sharing of a common hardware library of chiplets and their military applications. This require a thorough analysis of possible architectures, and the design of minimum one military application.

The proposed architectures should use EU-based technologies where available. Taking in account the existing EU manufacturing facilities and the civil programs such as Chips JU, proposed architecture should address:

• The non-dependence for defence systems to integrate this solution.
• The cost efficiency of the solution for low volume quantities (including NRE).

Particular attention should be placed on the power consumption, as this is an important issue for several applications.

The scalability of the architecture, in other words the possibility to adjust the SiP performances and/or functionalities through the addition or removal of chiplets in the design, should be presented and analysed.

In addition, proposals may address the integration of security features (cybersecurity) in the architecture, especially for protecting the resulting SiP.

Types of activities

The following types of activities are eligible for this topic:

Accordingly, the proposals must cover at least the following tasks as part of mandatory activities:

• Generating Knowledge:
  • Analysis of the current state of the art in different type of use-cases where chiplet-based architectures are implemented: processing, signal conversion, mixed-signal, or others.
  • Demonstration of the advantages of chiplet architectures for defence applications.
  • Identification of the available technologies (chiplet and integration) in and outside Europe which can or need to be used in chiplet-based components, with a description of the supply chain of each identified technology and an estimation of the technology benefits.
• Integrating knowledge:
  • Define electronic functions of military systems that can or should be realised with “chiplet” approach.
  • Having identified the available and needed technologies, identify benefits and risks for defence (defining shortfalls and possible dependency risks for each technology).
• Studies:
  • Explore the feasibility of chiplet architecture for defence:
    • Define which components-of-the-shelf can be used, which chiplets need to be developed and with which performances for a given feature.
    • Study the possible interface solutions between the chiplets.
    • Identify the best compromise between performance and sovereignty (security of supply), capacity for scalability (in memory, cells, number of processing cores…) and specialisation (compute accelerator, specific RF front-end…) from one defence application to another, security, and reliability.
    • Define the possible supply-chain, considering the use of EU foundries, especially for sensitive components (sensitive meaning subject to export control restriction) and the adequation of the supply chain to the targeted volume.
    • Identify cost drivers of the targeted architecture configuration.
• Design:
  • Definition of targeted performances: Define expected functions and their technical specifications for minimum one type of military application based on the “chiplet” approach.
  • Definition of the partial and risk reduction tests needed to validate the proposed design.
  • Proposed design must:
    • Integrate multiple (at least two) chiplets using different technologies or nodes.
    • Be compatible with the studied supply-chain optimisation.
    • Be compatible with the de-risking tests.
  • Evaluation of the final design in terms of performances and supply-chain optimisation on a representative demonstrator.

In addition, the proposals should cover the following tasks:

• Design:
  • The design should cover the scalability of the architecture (addition or reduction of the amount of chiplets of one single type in the architecture).

The proposals may also cover the following tasks:

• Design:
  • Design of more than one type of military application, with the associated specification, test definition, design and evaluation.
  • A design that addresses scalability of different features at the same time (for instance: adding memories chiplets and processing cores for a given architecture). This may cover specification, test definition, design, and evaluation.
  • Include security features.
  • Include features dedicated to the implementation of Artificial Intelligence in the system.
  • Software development may be included for the need of the evaluation of the demonstrator(s).

The proposals should substantiate synergies and complementarity with foreseen, ongoing or completed activities in the field of advanced packaging and advanced semiconductor nodes, notably those described in the call topics EDF-2022-RA-MATCOMP-PACOMP, DIGITAL-JU-Chips-2023-SG-CPL-3 and DIGITAL-JU-Chips-2023-SG-CPL-2, as well as other projects undertaken in the frame of the European Chips Act (such as Important Project of Common European Interest in microelectronics and communication technologies).

Functional requirements

The proposed product and technologies should meet the following functional requirements:

• The interface between chiplets should be compatible with different type of military applications (standardisation approach).
• The 2.5D or 3D integration should be based on EU capacities.
• The advanced packaging should be based on System-in-Package technology.
• The design should be made to optimise the power consumption of the system.
• The proposed design should be compatible with operations in harsh environment conditions of the targeted application.
• The design should be compliant with REACH and ROHS regulations.