Pilot line on advanced Packaging and Heterogenous Integration

REMINDER Call Deadline and Submissions:

The Deadline for submission is today 29 February 2024 at 17:00 Brussels time.

IMPORTANT: Only proposals submitted in each of the three interrelated calls will be eligible for evaluation

File Size increase:

Please be informed that the file size has been increased to 50MB for the Part B Submission. 

Page limit:

Please note that there are no page limits for the application but the consortia are encouraged to limit the narrative part of the application to 200 pages excluding the tables that are expected.

 The pilot line shall provide a platform for chiplet integration.

• This platform shall enable 2.5D and 3D heterogeneous integration for multiple core technologies (CMOS, Opto/RF) and devices (MEMS, Opto). It should enable chiplet integration of advanced nodes from external sources. As an important technology basis, fan-out and fan-in wafer level packaging should be developed for the different integration concepts. In the same way, through-x via and interposer technologies should be developed for the materials of interest. Those include silicon, glass, silicon carbide, polymers. Besides the latter materials, III-V materials should be part of the mix to enable interfaces with RF and photonics functions. And to enable a varied integration mix, diverse bonding technologies should be developed as building blocks as relevant, e.g. micro-solder-bump bonding, wafer-wafer-bonding, die-to-wafer-bonding and hybrid Cu-Cu bonding for extreme pad-pitches below 0.5 μm.

• The packaging technologies shall address the 200mm and 300mm wafer platforms since both are relevant for modern components. Where relevant, it is expected that the pilot line provides capacity for large scale organic interposer technology as panel integration as well.

• The developed technologies shall provide interfacing capability to semiconductor device integration. This means that different interface concepts and technologies should be developed for:

• RF and in particular millimetre-wave and beyond

• Advanced photonic functionalities, including integrated photonics

• Direct integration of sensors and MEMS solving the specific constraints of mechanical and thermal stresses

• Integration of novel energy-efficient non-volatile memory technologies

• Integration of novel functionalities with power electronic components

• System design is becoming an inherent component of advanced packaging. System technology co-optimization methodologies and tools should be developed through the pilot line to ensure they serve a holistic implementation of chiplet architectures through the system development flow (chiplet to system) where the package is an integral part of the system functionality. This comprehensive end-to-end design flow and methodology for chiplet-based advanced heterogeneous system integration will implement the Design-for-Testability, -Manufacturing, -Reliability, -Security methodologies as and where relevant. Those are essential enablers to ensure that the developed design and process flows are transferable to industrial environments and will be made available to a large community in cooperation with the design platform.

• Characterization, test and reliability are becoming increasingly complex when integrating multiple functional chiplets in a single package. Therefore, novel test concepts and technologies for function-, quality- and yield- optimization should be developed. This must inter alia cover non-destructive 3D imaging and defect metrology, improved electrical fault isolation, high-throughput destructive characterisation to isolate and study defects.

• This should be complemented by methods to fight against counterfeits, a growing concern while moving to chiplet-based systems.

• To increase the reliability of systems in the field, built-in self-test methodologies and functionalities should be proposed, and their integration developed.

The access policy from the different stakeholders to the pilot line should be defined in the proposal according to fair and non-discriminatory principles.

During the whole duration of the pilot line, the hosting entity and other partners should provide training to any European partner interested in designing devices based on the pilot line technology in order to use the full benefits of this technology, as well as for students for up- and re-skilling in order to attract new talents in the European semiconductor industry.

Collaborations: The proposed pilot line must facilitate the collaboration with other pilot lines, with design platforms and competence centres to allow contributions from other stakeholders that develop a strong expertise in a specific domain related to the topics of this pilot line.

The submission session is now available for: DIGITAL-JU-Chips-2023-SG-CPL-3(DIGITAL-JU-SIMPLE), DIGITAL-JU-Chips-2023-SG-CPL-1(DIGITAL-JU-SIMPLE), DIGITAL-JU-Chips-2023-SG-CPL-4(DIGITAL-JU-SIMPLE), DIGITAL-JU-Chips-2023-SG-CPL-2(DIGITAL-JU-SIMPLE)