Pilot line on advanced sub 2nm leading-edge system on chip technology

REMINDER Call Deadline and Submissions:

The Deadline for submission is today 29 February 2024 at 17:00 Brussels time.

IMPORTANT: Only proposals submitted in each of the three interrelated calls will be eligible for evaluation

File Size increase:

Please be informed that the file size has been increased to 50MB for the Part B Submission. 

Page limit:

Please note that there are no page limits for the application but the consortia are encouraged to limit the narrative part of the application to 200 pages excluding the tables that are expected.

 The proposed pilot line needs to work at all levels of the main technological steps:

• Development of the sub 2nm technology modules for enhancing the performance of the current technology, through reshaping the transistor architecture and introduction of disruptive materials and process technology options. . The main technologies to be developed need to be aligned with the advanced technology requirements expressed in international research roadmap(s) at device (logic, memory) and interconnect level.. They should be performed through a strong interaction between the process and design teams in order to optimize the sub 2nm SoC performance, and to deliver the research PDKs for each developed technology and process modules to that effect.

• Development of the crucial SoC-enabling process modules:

o Memories: The Pilot Line should include advanced NVM in the metal interconnections. These can offer new ranges of applications and would allow breakthroughs in new paradigms for computing. Novel emerging memory options should be explored to be validated by the pilot line users in collaboration with other pilot lines.

o System On Chip options: The Pilot Line should offer design and architecture options compatible with new 3D architectures, chip-on-wafer and wafer-to-wafer alignment technologies and efficient bonding techniques as well as high density advanced interconnects such as nano TSV’s to enable the 3D SoC at the die level and continue the performance increase and cost reduction enabled by sequential 3D monolithic integration for specific applications.

• Delivery of modules at pitch for next generation equipment and materials. R&D for such complex process technology should entail collaborative activities with equipment and material suppliers on base step, sub-module and module level innovations and mutual impact assessment of process steps in a flow. A substantial amount of characterization and fundamental studies of materials properties and interfaces is also required.

• Delivery of updated research PDKs

Once the technology and additional process module are mature enough the proposed pilot line should continuously deliver updated (research) PDKs of the developed technologies for technology assessment.

Any stakeholder must have access to these PDKs, and the additional modules through the Design Platforms, the Competence Centers and/or directly to the Pilot Line.

• Realization of early research demonstrations and (virtual) system exploration through MPW runs for European partners, according to an operational and access policy defined for the pilot line for the collaboration with those stakeholders.

The access policy from the different stakeholders to the pilot line should be defined in the proposal according to fair and non-discriminatory principles.

During the whole duration of the pilot line, the hosting entity and other partners should provide training to any European partner interested in designing devices based on the pilot line technology in order to use the full benefits of this technology, as well as for students for up- and re-skilling in order to attract new talents in the European semiconductor industry.

Collaborations: The proposed pilot line must facilitate the collaboration with other pilot lines, with design platforms and competence centers to allow contributions from other stakeholders that develop a strong expertise in a specific domain related to the topics of this pilot line.

The submission session is now available for: DIGITAL-JU-Chips-2023-SG-CPL-3(DIGITAL-JU-SIMPLE), DIGITAL-JU-Chips-2023-SG-CPL-1(DIGITAL-JU-SIMPLE), DIGITAL-JU-Chips-2023-SG-CPL-4(DIGITAL-JU-SIMPLE), DIGITAL-JU-Chips-2023-SG-CPL-2(DIGITAL-JU-SIMPLE)