Digital-ju-chips-2025-sg-ssoi

Create a sustainable accelerator open to all European stakeholders, providing access to state-of-the-art sSOI technology and manufacturing capabilities.

• Develop and standardize Process Design Kits based on validated sSOI substrate data, enabling designers to optimise their system-level architectures and meet the demands of next generation applications. These PDKs should support the transition to 7nm FD-SOI technology, ensuring readiness for high-volume manufacturing by 2030.

• Expand the capabilities of sSOI substrates to industrial-scale wafer production, ensuring low defect densities and improved manufacturing yields that meet the rigorous standards of advanced semiconductor fabrication.

• Drive the creation of intellectual property and strengthen Europe's production capacity in sSOI technologies, contributing to Europe's leadership in critical semiconductor markets.

• With a particular focus on complementarity with the FD-SOI pilot line, foster collaborative development through synergies with other Chips JU pilot lines, enhancing the overall innovation capacity and technological leadership of Europe in semiconductor technologies,

• Provide comprehensive training programs and skill development initiatives to equip European technologists and engineers with the expertise necessary for sSOI substrate integration and advanced semiconductor manufacturing

The proposed accelerator should address all levels of the key technological steps required to bring sSOI substrates to industrial scale:

• Development of industrial-grade sSOI substrates will focus on achieving low defect density, crucial for enhancing electron mobility and ensuring high-performance FD-SOI devices at the 7 nm node. This will involve refining strain engineering techniques, particularly to introduce a uniform global strain that can balance the performance for strained NMOS and relaxed PMOS transistors.

• Ensure compatibility with existing semiconductor manufacturing, the accelerator will refine process integration and optimisation. This includes improving epitaxial growth, wafer bonding, and defect reduction techniques to meet the requirements of advanced FD-SOI production processes.

Finally, the accelerator will promote collaboration across the semiconductor ecosystem, working with other pilot lines, as well as connecting to the design platform and competence centres, among others.